New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously

erek

erek

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Interesting

“With this design, X-Silicon’s C-GPU architecture can potentially run any type of CPU or GPU workload. X-Silicon claims to already have the Vulkan graphics API working with "fused GPU acceleration." This should greatly help with its development and adoption on Android devices.


As the new design is based on RISC-V, anyone can utilize the architecture without having to pay instruction-set royalty fees — unlike x86 and ARM. If it works as intended, the chips could shake up the microprocessor industry. The standard designs currently used are, in theory, not as flexible or capable as what X-Silicon claims to have created.


Whether it all works as well in practice as it does on paper remains to be seen, though we might not have to wait long to find out. Software development kits will reportedly be released to early partners sometime this year.”

Source: https://www.tomshardware.com/pc-com...-run-cpu-gpu-and-npu-workloads-simultaneously
 
erek said:
As the new design is based on RISC-V, anyone can utilize the architecture without having to pay instruction-set royalty fees — unlike x86 and ARM. If it works as intended, the chips could shake up the microprocessor industry. The standard designs currently used are, in theory, not as flexible or capable as what X-Silicon claims to have created.
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This part isn’t quite true, and it’s frequently misunderstood due to the common thoughts around open source.

The core architecture is open and free to use, but the ISA and instructions around that architecture is not and it is up to each implementing party to develop their own.

They make RISC out to be the free anybody can build one processor of the open and modern age but in reality it is something you need to put a lot of time and resources into. And it is why there are thousands of RISCV chips each custom and each proprietary.
 
Did they send out more news to their investors? Aside from the usual sources referring to the Aug 2023 post by x-silicon, I'm having a hard time finding anything else.
 
I feel like there is no universe that this pans out because it's impossible to make efficient
 
socK said:
I feel like there is no universe that this pans out because it's impossible to make efficient
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Quite the opposite, both AMD and Intel are showing off similar projects that greatly improve performance and efficiency and doing this is one of the secret sauces to the ARM platform as a whole that Apple has taken to the extreme with their M series chips.
 
erek said:

View: https://youtu.be/f6mPK3QCrBo?si=7pfs4b80uOnebDT5
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“Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V application processor with compelling performance density, seamless security and the artificial intelligence capabilities needed to support the compute and intuitive user experience needs for next generation consumer and industrial devices.

"The number of RISC-V based devices is skyrocketing with over 16Bn units forecast by 2030, and the consumer market is behind much of this growth" says Rich Wawrzyniak, Principal Analyst at SHD Group. "One fifth of all consumer devices will have a RISC-V based CPU by the end of this decade. ”

https://www.techpowerup.com/321286/imaginations-new-catapult-cpu-is-driving-risc-v-device-adoption
 
Well Bejing doesn’t like paying for old AMD and Intel hardware and they play to take over ARM didn’t pan out so this was the next step.

Was bound to happen eventually.
 
Lakados said:
This part isn’t quite true, and it’s frequently misunderstood due to the common thoughts around open source.

The core architecture is open and free to use, but the ISA and instructions around that architecture is not and it is up to each implementing party to develop their own.

They make RISC out to be the free anybody can build one processor of the open and modern age but in reality it is something you need to put a lot of time and resources into. And it is why there are thousands of RISCV chips each custom and each proprietary.
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What you have here doesn't make sense. Who is developing their own ISA? RISC-V is the ISA. The core architecture is what changes and isn't licensed.
 
kac77 said:
What you have here doesn't make sense. Who is developing their own ISA? RISC-V is the ISA. The core architecture is what changes and isn't licensed.
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I think he's referencing that RISC-V is (intentionally) very lax and flexible with custom extensions to the ISA. Makes sense for embedded and low power where you want to have functionality in hardware.
 
kac77 said:
What you have here doesn't make sense. Who is developing their own ISA? RISC-V is the ISA. The core architecture is what changes and isn't licensed.
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My explanation was bad but as to who, Imagination for one, their whole chip is pretty much a custom job, which is why they are selling their own licenses for it. But it also makes it incompatible with the base instructions.
But it’s going to get paired with the HarmonyOS and shipped out anyways so power to them. I’ll likely snag one in an SBC should they ever release it this way. I’m a throw away network but would be fun to tinker with all the same.
 
erek said:

View: https://youtu.be/f6mPK3QCrBo?si=7pfs4b80uOnebDT5
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SiFive Unveils the HiFive Premier P550 Out-of-Order RISC-V Development Board​

PRESS RELEASE by btarunr Today, 01:12 Discuss (0 Comments)
Today at Embedded World, SiFive, Inc., the pioneer and leader of RISC-V computing, unveiled its new state-of-the-art RISC-V development board, the HiFive Premier P550. The board will be available for large-scale deployment through Arrow Electronics so developers around the world can test and develop new RISC-V applications like machine vision, video analysis, AI PC and others, allowing them to use AI and other cutting-edge technologies across many different market segments.

With a quad-core SiFive Performance P550 processor, the HiFive Premier P550 is the highest performance RISC-V development board in the industry, and the latest in the popular HiFive family. Designed to meet the computing needs of modern workloads, the out-of-order P550 core delivers superior compute density and performance in an energy-efficient area footprint. Furthermore, the modular design of the HiFive Premier P550, which includes a replaceable system-on-module (SOM) board, gives developers the flexibility they need to tailor their designs.

1712669748879.png
 
erek said:

SiFive Unveils the HiFive Premier P550 Out-of-Order RISC-V Development Board​

PRESS RELEASE by btarunr Today, 01:12 Discuss (0 Comments)
Today at Embedded World, SiFive, Inc., the pioneer and leader of RISC-V computing, unveiled its new state-of-the-art RISC-V development board, the HiFive Premier P550. The board will be available for large-scale deployment through Arrow Electronics so developers around the world can test and develop new RISC-V applications like machine vision, video analysis, AI PC and others, allowing them to use AI and other cutting-edge technologies across many different market segments.

With a quad-core SiFive Performance P550 processor, the HiFive Premier P550 is the highest performance RISC-V development board in the industry, and the latest in the popular HiFive family. Designed to meet the computing needs of modern workloads, the out-of-order P550 core delivers superior compute density and performance in an energy-efficient area footprint. Furthermore, the modular design of the HiFive Premier P550, which includes a replaceable system-on-module (SOM) board, gives developers the flexibility they need to tailor their designs.
View attachment 646519
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Is that a horizontal Slocket? Everything old really is new again. 🤣
 
DanNeely said:
Is that a horizontal Slocket? Everything old really is new again. 🤣
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FPGA integrates hard RISC-V cores​

1713121457627.png


“The 32-bit hardened RISC-V block (RISCV321 with M, A, C, F, and D extensions and six pipeline stages) offers a Linux-capable MMU, FPU, and custom instruction capability. Paired with an Efinix Sapphire SoC, the Ti375 FPGA helps designers turn a tiny chip into an accelerated embedded compute system.”

https://www.edn.com/fpga-integrates-hard-risc-v-cores/
 
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