AMD "Navi 31" Memory Cache Die Has Preparation for 3D Vertical Cache

[erek]

Could be cool. Maybe RNDA4 will have some of this 3DVCache:

"In microscopic observations, Wassick noticed structures on the MCD which he thinks look like an array of through-silicon vias (TSVs), of the kind used in "Zen 3" and "Zen 4" CCDs, to wire out stacked 3D Vertical Cache memory on the L3D (L3 cache die). If the theory holds up, it could be possible for AMD to increase the L3 cache segment size per MCD from 16 MB, and the GPU's overall Infinity Cache memory size. With its RDNA2 graphics architecture (RX 6000 series), AMD significantly enlarged on-die caches on its GPUs, particularly the last-level L3 cache, even giving them the special branding of "Infinity Cache," claiming that they had a big impact in lubricating the memory sub-system, letting GPUs with 256-bit memory buses compete with NVIDIA GPUs with wider 320-bit to 384-bit interfaces."

Source: https://www.techpowerup.com/304206/...che-die-has-preparation-for-3d-vertical-cache

 

[Lakados]

I’d like to see the microscope images. They aren’t posted anywhere I can find though.

 

[blackacidevil]

Wonder if this might be a clue for the rumored 7950 XT/XTX and 7990 XTX refresh models.

 

[Wat]

This isn't new. Amd talked about this in one of thier reveals a while back. The cost/benefit wasn't enough for them to release models with the extra cache.