Manny Calavera
2[H]4U
- Joined
- Jun 10, 2004
- Messages
- 3,986
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Quote:Originally Posted by BeardyMan
Are you expecting them soon or???
__________________Join Date: Sep 2002
Posts: 5,028
Originally Posted by s7e9h3n
Yes...very soon...along with B2 Barcelonas
He gets the chips that you design before most people get them.I'm not familiar... who's this s7e9h3n fellow? He seems awfully popular there.
Same exact super pi as me, except im at 2.7 and thats at 2.4. Though I dont know how to account for the memory differences. Mine is DDR500 2.5-3-3-7 (highest I can get at 1t). Discounting all memory differences though its about 13% faster clock per clock than my 939 in superpi.
No it was not 100% fare,but still.
It shows that its not the Care2 beater they said it would be,and certainly not the Penryn beater eithier.
Lowering the ram timings to T1 instead of T2 will not make a any real difference.
No it was not 100% fare,but still.
It shows that its not the Care2 beater they said it would be,and certainly not the Penryn beater eithier.
Lowering the ram timings to T1 instead of T2 will not make a any real difference.
That's cool and all, but it doesn't do much good( I can see a little) if intel still keeps a better price/performance ratio
This is like the whole HTT vs FSB argument. It doesn't matter if what AMD is doing is more elegant if Intel can get superior results from their less elegant solution.Uhhhh YES, it does alot of good for AMD. If this software can enable AMD quadcores to run much more cooler and efficiently by adjusting power or clock frequencies for specific tasks than Intel's offerings while still holding a good price performance ratio, it's a win/win situation, period. This software is putting AMD's new superior multi-plane power and clock distribution system to very good use, I know system admins and power users will love it.
This is like the whole HTT vs FSB argument. It doesn't matter if what AMD is doing is more elegant if Intel can get superior results from their less elegant solution.
I eagerly await hard numbers on both performance and power consumption.
Temperature control and overall stability are two reasons.It's just looks "cool" but isn't practical.
Whats the point of cutting down clocks when the power state is still Dependant on the highest core.
You guys do know that Independent Voltage doesn't work on separate cores right?
Even if the cores are different clocks, all the cores have the same voltage as the highest core.
If core 3 is 3.3Ghz but is using 1.4V, then all 4 cores will be 1.4V even if they are at a lower speed.
It's just looks "cool" but isn't practical.
Whats the point of cutting down clocks when the power state is still Dependant on the highest core.
the SPP / IPP splits power between the IMC / 4Cores, not core to core from what I read,Not true. Each core has it's own voltage plane. That is one of the biggest differences between AM2, and AM2+..... Besides I think this will really help overclockers out as well. If you have 4 cores, and one of them ias capable of hitting 3.4GHZ, and another is only capable of hitting 2.9GHZ, you can clock them separately without being held back by the slower core.
Dynamic power dissipation is typically a linear function of clock frequency.Whats the point of cutting down clocks when the power state is still Dependant on the highest core.
Not true. Each core has it's own voltage plane. That is one of the biggest differences between AM2, and AM2+..... Besides I think this will really help overclockers out as well. If you have 4 cores, and one of them ias capable of hitting 3.4GHZ, and another is only capable of hitting 2.9GHZ, you can clock them separately without being held back by the slower core.
Dynamic power dissipation is typically a linear function of clock frequency.