Myths about Dual Channel

[RawsonDR]

It seems there's a lot of speculation hovering around 'Dual Channel' technology and how exactly it works. Because of the way Dual Channel is marketed, and perhaps also the human predilection for symmetry, many people believe that one must use sticks of varying levels of similarity. Same size, same company, same model, or even same production batch for the 'Dual Channel' process to work (or work best). I've always disregarded such dramatic obsession as myth but never had any evidence to prove either way.

However to get the ball rolling I did a few tests on a secondary system of mine.
Gigabyte GA7N400 Pro2, Barton 2500+, 1x512 OCZ PC3500 Double Sided, 1x256 Crucial Tech PC2700 Single Sided
My results:



The point of this thread is to help clear away speculation that builds up around things like this, and to replace it with fact instead. I've shared my experience, and I'd like to hear from some others who have either corollary or contradictory points of their own.
More specifically, is there any evidence to support the marketing of 'matched pair' dual channel memory?

Full Cpu-Z shots -> Memory tab | Slot 1 | Slot 2
edit: Prime95 screenshot added.

 

[(cf)Eclipse]

awesome, thanks rawson.
jsut out of curiosity, can you show some bandwidth figures too?

also, there's one thing matched pairs are good for if done properly: oc'ing
get two sticks.. normally one is a lot better than the other. if it's an enthusiast company worth their salt, maybe both sticks have a similar top end, thus got put together?

other than that, it's useless.

 

[shaihulud]

memory particulars are by no means speculated. what many have turned it into is an ignorant user commenting on their relative experience as fact, which is a fallacy and disconcerting. memory specifics are noted throughout the industry, and the user must be compliant to them.

one fact you must remember is that the nforce2's controller is not a dual channel. it is two controllers that are segregated and arbitrated. these controllers will work in conjunction to perform similar to dual channel.

the nforce2 core logic will use the smb to read the spd, and set the configurations in the bios. this is of course, if it is set for auto. the read is always done from the first installed bank. this will be the timing set for all installed dimms. if bank 1 has a dimm installed that cannot be complaint with the timings, set by bank 0, it can cause errors when accessed. these errors can be exacerbated, or may not be exhibited till certain programs are used. e.g. many users exhibited gpf's with "non-compliant" memory configurations and using unreal 2003/04. all though all criteria was met , e.g. psu load, memory was indeed the issue. when proper memory, not certified for dual channel, but usage on the motherboard, was installed issues were not experienced.

if it is a ganged 128bit controller, such as the athlon 64, it will not be as forgiving. many woes were experienced to non-compliancy with the 875p (ganged). by all means the user configuring the system needs to make sure that the memory is compliant for use on the motherboard being used. all memory, in theory, will run dual channel, for it is how the controller reads the array of bits. but the memory then needs to be compliant with each other, this is where PR comes into play with the laws of economics.

what you are paying for is the guarantee that the memory purchased is compliant, and matched on all configurable possiblities. bin A and bin B could have been used to frabricate the dimms. however, bin B may work at a different timings in one configurable range than bin A. you are paying for the fact that it has been tested and confirmed that the dimms will work, if compliant to the motherboard, in dual channel with the same timings. there is a bit of PR to this, however, there is some truth to it.

i would highly suggest other means of testing your system. just showing that it is "working" is by no means scientific,and you also must consider that the nforce2 is not a ganged 128bit controller. perhaps, giving prime95 a try. you can use memtest+, but it is not as thorough as some think. if you do chose to test it make sure that you do and extended test and for at least 10 passes. playing games such as doom3 can test well for stability, as many via cor logic user can note, etc.

note: cpuz will read the spd of the dimm which is not the timings used. you will need to read "timings" to see what it is set to.

 

[RawsonDR]

Well here is the Sandra result.

However this was done over Remote Desktop and I have no way of knowing if that could impact the performance. Also the chip is underclocked (multiplier only) to 166x10.

Do the results look normal to you?

 

[RawsonDR]

the nforce2 core logic will use the smb to read the spd, and set the configurations in the bios. this is of course, if it is set for auto. the read is always done from the first installed bank. this will be the timing set for all installed dimms. if bank 1 has a dimm installed that cannot be complaint with the timings, set by bank 0, it can cause errors when accessed. these errors can be exacerbated, or may not be exhibited till certain programs are used. e.g. many users exhibited gpf's with "non-compliant" memory configurations and using unreal 2003/04. all though all criteria was met , e.g. psu load, memory was indeed the issue. when proper memory, not certified for dual channel, but usage on the motherboard, was installed issues were not experienced.

Actually, this is a very good argument for my case. If memory is run out of spec and then used to test dual channel, is one to conclude that there are inherent incompatibilities in the Dual Channel config relating to mismatched sticks?
No, of course not. That would be the exact speculation that we are trying to avoid.

by all means the user configuring the system needs to make sure that the memory is compliant for use on the motherboard being used. all memory, in theory, will run dual channel, for it is how the controller reads the array of bits. but the memory then needs to be compliant with each other, this is where PR comes into play with the laws of economics.

I think you need to clarify some of your points for me because I am having trouble understanding. The above quote, for example, seems to be right in line with my argument. In what ways, do you mean, need the memory be compatible with each other? What comes to my mind is things such as buffering, error checking, and speeds. But this goes without saying. I will not attempt to argue that I can run PC2100 RAM at PC3200 speeds in Dual Channel at stock voltage, or that I can run a stick of ECC RAM in Dual Channel with a stick of non-ECC RAM, or anything of the sort. But if this fact were to argue against my point in the original post, then you would have to show me RAM that does this in single channel.

You have a valid point when you tell me that my testing methods are not scientific, but I never made a claim that they were. They were tests to 'get the ball rolling' on this discussion and advertised as such, and if you or anyone has points to make invalidating my 'evidence' I need to hear them so I can retract my argument. (thats why I posted)

note: cpuz will read the spd of the dimm which is not the timings used. you will need to read "timings" to see what it is set to.

It will do both. View the first screenshot.

edit: I forgot to ask you where I can read more on the Dual Channel specification in regard to its implementation in the nforce2 chipset. I can't easily dismiss my motherboard as a Dual Channel candidate when it obviously carries the claim that it is.

 

[(cf)Eclipse]

Do the results look normal to you?

yeah, i typically got 90-91% efficiency with my a7n8x in dual channel ddr400. (~2900mb/s)

shaihulud, if definitly sounds like you know what you're talking about. that's a very impressive post. however, i agree with rawson. some linkage to more data on how the nf2 chipset (and a64 memory controller) work would be nice

 

[shaihulud]

Actually, this is a very good argument for my case. If memory is run out of spec and then used to test dual channel, is one to conclude that there are inherent incompatibilities in the Dual Channel config relating to mismatched sticks?
No, of course not. That would be the exact speculation that we are trying to avoid.

as i said, this [nforce2] is not a ganged 128bit controller. erroneous bahavoir exhibited is going to be different when compared to such. it is two memory controllers, working in conjunction, totally segregated. so, it is NOT a true dual channel controller. try what you are doing in a athlon 64 or 875p, and you will come accross something for your research. nvidia does not post whitepapers as like intel does, but this has been known since the nforce1.


http://www.nvidia.com/object/feature_dualddr.html

Highest memory bandwidth: DualDDR combines the power of DDR400 with two independent memory controllers, which yields a staggering 6.4GB per second of memory bandwidth—twice the memory bandwidth of other DDR400 chipsets. Increased memory bandwidth delivers better system and graphics performance, resulting in more overall productivity.

Lowest latency: Both memory controllers operate concurrently with each other to hide latencies associated with typical chipsets. For example, controller "A" reads or writes to main memory while controller "B" prepares for the next access, and vice versa. As important is the second-generation DASP (dynamic adaptive speculative preprocessor), which has been re-architected for improved performance.

I think you need to clarify some of your points for me because I am having trouble understanding

to clarify, if possible. the ram must be tested and compliant: http://www.cmtlabs.com/default.asp http://usa.asus.com/products/mb/socket939/a8v-d/overview.htm another example, scroll down to the bottom of page. main issue, single or dual.

the installed dimms have to be able to tolerrate the timings set by the governing dimm. this is where most of the issues come from in dual channel, specially ganged 128bit controllers. because the access to the array is over 2 dimm banks, x virtual banks, if any. operating at different timings will, and can cause problems. you are paying for this guarantee, that they are compliant with each other.

But if this fact were to argue against my point in the original post, then you would have to show me RAM that does this in single channel.

start from the top of this post....again. all ram is "dual channel" capable (which, i said previous post), but you are not understanding the intrinsic characteristics of how the memory is operating by a particular controller.

It will do both. View the first screenshot.

i know it will, as i said: note, cpuz will read the spd of the dimm which is not the timings used. you will need to read "timings" to see what it is set to.

edit: I forgot to ask you where I can read more on the Dual Channel specification in regard to its implementation in the nforce2 chipset. I can't easily dismiss my motherboard as a Dual Channel candidate when it obviously carries the claim that it is.

its PR! core logic knowledge is a fav, and my forte.

You have a valid point when you tell me that my testing methods are not scientific

download prime95 and run it in "torture test" mode. see if you come across any errors. you should have at least started with memtest+ before wanting to debunk. sandra will not prove a thing. http://www.mersenne.org/freesoft.htm
http://www.memtest.org/

 

[RawsonDR]

Honestly, I'm not trying to turn this thread into a pissing contest. But I feel you are missing some of my points. This is evident in the following example.

the installed dimms have to be able to tolerrate the timings set by the governing dimm. this is where most of the issues come from in dual channel, specially ganged 128bit controllers. because the access to the array is over 2 dimm banks, x virtual banks, if any. operating at different timings will, and can cause problems. you are paying for this guarantee, that they are compliant with each other.

But if this fact were to argue against my point in the original post, then you would have to show me RAM that does this in single channel.

start from the top of this post....again. all ram is "dual channel" capable (which, i said previous post), but you are not understanding the intrinsic characteristics of how the memory is operating by a particular controller.

If a dimm is operating out of its spec, that is an issue with the DIMM and the user and not the dual channel configuration. Your argument "the installed dimms have to be able to tolerrate the timings set by the governing dimm" is valid both when referencing dual and single channel configuration. Is it not? So how is it an argument against my point that any incompatibilities noted are inherent in systems other than the dual channel config itself? (i.e. dual channel itself is unbiased)

If there is a difference between K7 and K8 "dual channel", then at most this argument is only applicable to K7. But that still makes it applicable. At some point I will test on an nforce3 platform and then we will have that information. That's all this thread is about: information.

It will do both. View the first screenshot.

i know it will, as i said: note, cpuz will read the spd of the dimm which is not the timings used. you will need to read "timings" to see what it is set to.

Are you trying to say that THIS picture is displaying the SPD table and not the actual timings?

Prime95 is currently at >7 hours in the Blend torture test. My sandra screenshot was not in reference to you or to stability, please don't take it as such. I will post the Prime screenshot later today.

 

[#Will]

Is it possible to run 2 double-sided sticks, 1 being 512MB and 1 being 1024MB (1536MB total in 2 slots) in dual channel? Both sticks will be Geil Value Series DDR400 on an 875P board and overclocking isn't a factor.

 

[RawsonDR]

Is it possible to run 2 double-sided sticks, 1 being 512MB and 1 being 1024MB (1536MB total in 2 slots) in dual channel? Both sticks will be Geil Value Series DDR400 on an 875P board and overclocking isn't a factor.

Well that's sort of what I'm trying to figure out. I only know of my experience and am curious to hear from others. However I will venture a guess to say that it will work. However your motherboard might have its own specifications on how that config would work (i.e. sometimes too much RAM means it must run slower), but I know nothing about Intel boards.

 

[shaihulud]

Honestly, I'm not trying to turn this thread into a pissing contest. But I feel you are missing some of my points. This is evident in the following example.

im not thinking that it is a pissing contest. im trying to complement the data, if possible.

If a dimm is operating out of its spec, that is an issue with the DIMM and the user and not the dual channel configuration

in which can effect dual channel. if dimm bank x is not equal with dimm bank y, then there can be issues with a ganged 128bit controller. x+y=the array of memory and for operation x must equal y, which is the reason for matched pair access. it should be noted that at 200mhz timings are very specific, this is when issues will be most prevalent. at lower FSB settings errors may not or could not surface. this is why i am saying do this with an 875p or athlon 64, if possible. the athlon 64 may exhibit errounrous behavoir with lower mem clock speeds.

Your argument "the installed dimms have to be able to tolerate the timings set by the governing dimm" is valid both when referencing dual and single channel configuration. Is it not?

correct

So how is it an argument against my point that any incompatibilities noted are inherent in systems other than the dual channel config itself? (i.e. dual channel itself is unbiased)

dual channel is how the array is mapped, and accessed. so any memory can be accessed in a dual channel. how the logic [mem controller] does this, will vary from one to the other that is used. remember the memory is the only point of failure, considering that the nothing else is defective. many reads at a memory forum, like crucial's, will note that even the "dual channel" and "compliant" memory have issues.

If there is a difference between K7 and K8 "dual channel", then at most this argument is only applicable to K7

depends on the core logic [k7], and obvious for the athlon 64. however, the argument applies to all that are dual channel capable, including p4 core logics. one interesting note, from memory banks to memory controller it is 128bits, or 64bits with nforce1/2. from the FSB to the processor it is 64bits. the athlon64 is obvious.

Are you trying to say that THIS picture is displaying the SPD table and not the actual timings?

that is displaying the timings in usage, as i have said before. the other pictures are reading the spd, and outputting the configurations supported. note crucial's reported the supported speed, and configurations: http://img23.echo.cx/img23/5774/mem36ig.png


RawsonDR, you may find this a good read through. http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31411.pdf page 14 will show the mapping of the memory in 128bit mode.

Is it possible to run 2 double-sided sticks, 1 being 512MB and 1 being 1024MB (1536MB total in 2 slots) in dual channel? Both sticks will be Geil Value Series DDR400 on an 875P board and overclocking isn't a factor.

http://www.intel.com/design/chipsets/applnots/252730.htm this will explin it faster than i can type it.

 

[RawsonDR]

If a dimm is operating out of its spec, that is an issue with the DIMM and the user and not the dual channel configuration

in which can effect dual channel. if dimm bank x is not equal with dimm bank y, then there can be issues with a ganged 128bit controller.

What we are talking about now is DIMM module instability. If a DIMM is giving out errors, then there will be problems with memory in general for that exact reason, no matter whether its being accessed through two channels or one. This is my argument: the problem discussed here is not a dual channel inherent flaw.

Its like washing a car with two hoses instead of one. If one hose is spitting out dirty water, you're gonna have problems. The problem is not that you are using two hoses, however. Conversely, if both sticks of RAM are able to put out good data, alone, at 200mhz, then I don't see a problem whether they are 'matched pairs' from the same factory or not. They will put out good data together, as well.

If there is a difference between K7 and K8 "dual channel", then at most this argument is only applicable to K7

depends on the core logic [k7], and obvious for the athlon 64. however, the argument applies to all that are dual channel capable, including p4 core logics.

You missed my point here. When I said "this argument" I was referring to my argument such as in my tests where I ran two sticks (different size, brand, spd, etc) in dual channel and they seemingly work fine (no, I am not saying this is proven, I merely said my argument is such). In other words, the fact that K7 and K8 architecture is different only says my initial findings do not apply to anything K8; for that we'd need more tests. It does not invalidate the findings all together. This basically goes without saying.

that is displaying the timings in usage, as i have said before. the other pictures are reading the spd, and outputting the configurations supported. note crucial's reported the supported speed, and configurations: http://img23.echo.cx/img23/5774/mem36ig.png

Yes, this is fact, and unquestioned. What I am trying to figure out is what point you were ever trying to make in regard to this sub-topic of our conversation. I never made any claims that the spd table was actual timings or vise versa. In your initial note "cpuz will read the spd of the dimm which is not the timings used. you will need to read "timings" to see what it is set to." you make it sound as if I only showed one and made a claim that it was something else, when in fact all the information was posted and accessible from the beginning.

Edit: First post has been edited to include new screenshot.

 

[mavalpha]

Is it possible to run 2 double-sided sticks, 1 being 512MB and 1 being 1024MB (1536MB total in 2 slots) in dual channel? Both sticks will be Geil Value Series DDR400 on an 875P board and overclocking isn't a factor.

In my understanding, no they won't work in dual-channel. I'm sorry if I'm perpetuating a myth, but I was under the impression that the most critical element in DC mode was the raw capacities of the sticks. Frequencies and timings could be manually overridden in BIOS, but capacities and number of banks couldn't. (In the case of the NF2- accepted as not true DC- this should be replaced with capacities of the controllers, hence the option to run 2x256 in one channel and 1x512 in the other)