Prescott Extreme Edition?

[coz]

I've just had a scary thought. Sooner or later (or never ever?) we're going to see a Pentium 4 Extreme Edition (P4EE) based upon the Prescott (PSC) core. What's scary about that you ask? One word - transistors. The original P4EE was based upon the Xeon MP 'Gallatin' 2MB L3 core - basically a Northwood (NWD) with 2MB of L3 cache. The Northwood core weighs in at 55 million transistors, add to that the 114 million L3 cache transistors and you get a P4EE with 169 million transistors. Now, PSC weighs in at 125 million transistors already, add that 2MB L3 cache to it and you get a Prescott Extreme Edition (PSCEE) with 239 million transistors!! Plus, it may be more than a 2MB L3 cache we get with PSCEE. There's a 90nm Xeon MP core codenamed Potomac that contains a huge 8MB L3 cache!! I'm sure we won't see that but the last P4EE was basically a Xeon 'Gallatin' MP, which Xeon is the PSCEE going to be?

Anyway, back to those 239 million transistors.....

Intel's new 90nm process has hardly been the roaring success we imagined it would be, based on previous process shrinks (0.25 micron -> 0.18 micron -> 0.13 micron). In fact it's more roaring inferno than roaring success. The main problem is heat - the Prescott is suffering from bigtime power leakage - it's power incontinent!! Check page 2 of this article over at Ars-Technica for a good explanation of power leakage. With 239 million leaky transistors we could be looking at some huge power dissipation numbers for PSCEE. Of course, with the different role of L3 cache transistors in the die, things may not be quite so bad.

When those 114 million transistors got added to the Northwood core to make the original P4EE we saw Intel's TDP (the recommended power dissipation in watts that the heatsink+fan needs to cope with) numbers for the 3.2C and 3.4C increase by 12% and 15% respectively (when comparing P4EE to their NWD versions). That's a modest increase for a 200% increase in the transistor count so maybe PSCEE won't be so bad? A 15% increase in the PSC 3.4GHz TDP would equal about a TDP of 132W for the PSCEE 3.4GHz and they must be looking at releasing faster versions than that.

But with the power leakage problems Intel currently have with PSC they may be keeping PSCEE waiting in the wings until they're fixed? The E-0 stepping is due later this year and that will fix a lot of the power issues with Prescott, that may be enough to roll PSCEE out the door?

Another possibility is that they won't release a PSCEE. The Pentium 4 720 is going to be released in Q4 this year. That will be a 3.73GHz Prescott with 2MB of L2 cache (up from 1MB) running on a 1066FSB. It's not an extreme edition but it's sort of semi-extreme and I'd rather have a 2MB L2 cache than a 2MB L3 cache. With the 720 around, Intel may figure they don't need a PSCEE? Anyway, that's something to think about.



For those of you who kind of checked out earlier because I was boring the crap out of you - me say Prescott hot, Prescott extreme edition - double hot. That is all.

 

[JetUsafMech]

I'd have to go with Intel not releasing a Prescott EE for the reason you stated, the 720 coming in the fall w/ 1066 FSB and 2MB L2. A Prescott EE would be an interim chip at best, with 720 waiting on its heels. Really, what could they do to Prescott to earn the EE tag? I am very curious about the E-O stepping, though.

 

[FreiDOg]

Cache, especially L3 won't add much to the TDP figures. Gallatin EE has a TDP only about 10% higher than NorthWood for the 3.2ghz chips.

SRAM cells donn't have to have those insane switching frequencies you need in a multi gigahertz ALU. You can have multiple clock cycle delays, and the tasks don't have the complexity (or the depth) of what you'd find along a critical path.
That lets you use much better insulated, much wider 'gapped,' much slower switching, and as a consequence, much more power efficient transistors.