To decouple or not to decouple...

[AreEss]

Okay, I have an interesting little monstrosity going here, and I'm running into questions I don't know the answers to. (Big surprise there.)

Got a TI TUSB5052; it's an 8052, 5 port USB (1 root/4 child), 2 serial, 7 GPIO PQFP100.
Still with me? No? Me neither.

So I have this on a 4 layer PCB, with the +3.3 coming from the motherboard, +5 from an HDD connector to the power plane, +12 to it's own little space.

Now, the TUSB5052 has four pins per USB connection, but they aint PWR D+ D- GND. They're D+ D- OLOAD and PWR. Well, I'm going root to mo'board connector, so that's said and done. (Using the reference PUR design.) OLOAD and PWR are going unused, since I'm pretty sure I don't even need them.

So I'm putting the remaining four USB ports to D+, D-, then a via to ground plane, and a via to the +5V power plane. The question is, right now, I just have it laid out as straight traces on the power plane. Should I be decoupling the USB ports with your typical 0.1uF capacitors? Should I leave them straight? Should I use bigger capacitors?

TI's docs are ass in terms of electrical characteristics and recommendations. Very frustrated minds want to know.

 

[Mohonri]

Decoupling capacitors are a good thing...usually. As long as the capacitors are the right size so they don't smooth out your signal or totally kill it outright, they're good short-circuit protection. You may want to hook up an o-scope to make sure the signal gets through ok. If you're sure that nothing is going to try to over-volt your chip (repeat after me: "We love ESD!"), you can probably just leave the traces straight.

 

[chopsuwe]

There is no such thing as too much decoupling. Leave space for a 0.1uF on each port, a bigger cap, maybe 10uF and 0.1uF on each of the power supplies. The 0.1uF removes high frequencies, the 10uF lower ones. Try testing it without the caps and see how it goes. Leaving provision for all eventualities is good practice and a lot easier than redesigning the board later

 

[AreEss]

That's what I was figuring; 0.1uF along the bottomside with an 'exposed' trace between the USB ports should be sufficient. (Tore apart a USB hub or two, they're all 0.1uF.) I'm still figuring out how to decouple the entire 5V plane, but not sure I should; it's fed directly by the PSU and all the parts taking +5 don't start freaking till 7V (excepting the USB.) There definitely isn't room to decouple those properly either; frigging 0.5mm spaced 0.25mm contacts.

Any suggestions?

 

[SacLANd]

normally you would decouple where where the power enters the PCB.
then i would suggest decoupling each chip.
a fun way to do it is if there is enough room, put the cap underneath the chip. or buy a socket for it and put it in the empty space in the socket.

 

[AreEss]

Well, I can make that work easily enough. Here's how it's setup:

+5V ----- Bigass Via to Power Plane
GND ---- Bigass Via to Ground Plane
GND ---- Bigass Via to Ground Plane
+12V ---- Filled Area

The +5V and one GND are top layer, and +12V and GND are bottom layer. So I just trim the traces so that it goes through a capacitor. The question is, how big a capacitor?

I'm guessing I should be making a count of how much draw I've got, and following some sort of semi-standard equation?

(edit, 'cause I forgot) If you take a look at the TI TUSB5052, you can see why decoupling is extremely difficult. I suppose I could probably decouple the +3.3V, but I was figuring I'd just shove a diode in.

 

[AreEss]

Up we go for further advice. Here's what I was figuring to do...

+5VIN --- 1.5uF Polarized --- Power Plane
+12VIN --- 0.5uF Polarized --- Power Traces
+3.3VIN --- 1uF Polarized --- Power Traces

Power to USB: Power Plane -> 0.1uF SMD -> USB Port -> 0.1uF SMD -> USB Port -> etc..

Figuring the draw as follows;

+5V = ~2A peak
+12V = 350-500mA peak (Firewire port, I'm probably off there.)
+3.3V = ~750mA peak (will need to check; the thermal sensors are also +3.3V, but I can also run them +5V)

How's that sound?

 

[Kritter]

Decoupling the datalines will change your rise/fall times and totally screw with your northbridge's head.

 

[gee]

Why go polarized for ~1uF parts?

check out MLCC ceramics from panasonic, AVX, KOA, murata, etc... almost every ceramic company on earth makes a 1uF/25V X5R ceramic in an 0805 case. And if you're decoupling chips, you'll need the low ESR these things offer.

Also, check out the book "high speed digital design: a handbook of black magic" by howard johnson... it's the bible for discussions like this.

 

[AreEss]

Decoupling the datalines will change your rise/fall times and totally screw with your northbridge's head.

That's D+/D-. There's a seperate +3.3V Vcc which can be safely decoupled without tweaking rise-fall. Actually, if it's not decoupled, it'll foul rise-fall both directions.

Why go polarized for ~1uF parts?

"Why not?" I'm paranoid. I don't want any chance of things going awry and causing damage. Plus...

check out MLCC ceramics from panasonic, AVX, KOA, murata, etc... almost every ceramic company on earth makes a 1uF/25V X5R ceramic in an 0805 case. And if you're decoupling chips, you'll need the low ESR these things offer.

The bulk are Nichicon tiny-case (3x2) 0.1uF's that're good to 25V. I'm debating fused for the 5V/12V, just for safety's sake.

I'll check out that book later this evening. Bear in mind, I really have no real experience or background in this stuff, so most books end up being over my head. (Small words, damnit!)

 

[gee]

"Why not?" I'm paranoid. I don't want any chance of things going awry and causing damage. Plus...

There's no advantage in using polarized caps.

And for decoupling, ceramic caps are superior to all others... their ESR/ESL numbers are far better than any polarized capacitor - tantalum, electrolytic, etc.

 

[AreEss]

There's no advantage in using polarized caps.

Fair enough, scrap the polarized then.

And for decoupling, ceramic caps are superior to all others... their ESR/ESL numbers are far better than any polarized capacitor - tantalum, electrolytic, etc.

Well crap. They're also bigger than the others. And I have a very, very finite amount of space to work in. Literally, I have to stack the 5 USB ports right on top of eachother. There's 1.25mm clearance between them, which is just barely over absolute minimum and short on recommended.

I'll see if I can throw up the basic PCB design in a bit; lots have to be cut out, because there's some NDA'd IC's on the right side.