When will Intel go native dual/multi core??

[Tripp17]

Hey all, i just wanted to say that i love my e6600, it clocks like a true champ and its value is unbeatable. That said, when the hell is intel going to come out with a native dual core processor? Or a native 4 core processor? Yes, the performance is good in c2d, but would be really special if it was native. If it were native and had a memory controller on it you would see MAJOR improvements across the board. Word has it that the processors after the new 45nm will have there own memory controller, but i wonder if itll be native or just 2 cores "bolted" on a chip and called dual core. I can understand 4 core chips being 2 dual cores on a chip, but i really thought after the pentium Ds that they would be native dual cores. AMD is coming out with native 4 core processors and supposedly outperform intels 4 core processors by 40%!! Heres a qoute for ya, “We expect across a wide variety of workloads for Barcelona to outperform Clovertown by 40%." http://www.xbitlabs.com/news/video/display/20070126134038.html
Just a thought, i love the turn around Intels made, but i really whant a native dual core solution, and a native 4 core solution would be amazing. As always, i have no brand loyalty and will go where the performance is.

 

[Michael Daly]

when the hell is intel going to come out with a native dual core processor? Or a native 4 core processor?

The C2D is dual core on a single die. The current quad core are two dual core dies in a single package. The first quad core single die is due later this year - I don't remember exactly when, but ISTR Q2 for samples to OEMs. I'm sure you could find out easily with a web search.

 

[Tripp17]

I thought that the c2d was native too untill i read this from this website, "Quad-core will again be achieved from putting two dual core Penryn cores on one package. Continuing with their somewhat criticized strategy of simply packaging multiple chips together for their Duo and Quad product lines, instead of investing in new true native multi-core designs, Intel stated that the company intended to continue using its current multi-chip packaging and had no intention of moving to a single chip multi-core design at this time." Its in the conclusion section of the 45nm review on Hardocp. Thats why i asked.

 

[Mabrito]

OMG this native stuff is B/S.

The dual core Core 2's are "native." They share the same cache. The quad core Q6700 and Q6600 are two Core 2 cores on one chip.

The 45nm is going to be the same way. If its a dual core, its going to be "native" and if its quad its going to be 2 cores on one chip.

It does not make a damn difference if its native or not. If the performance is there then who gives a damn. It just AMD started claiming, "Well are quad cores share the same cache and are "native" and Intel's quads are not." Then every one hails AMD for there "native" design and bashes Intel for there non "native" design (not a bash to AMD as im looking foward to there new gen as its coming out in the time im building a new computer).

Ok im done ranting.

 

[Manny Calavera]

OMG this native stuff is B/S.

The dual core Core 2's are "native." They share the same cache. The quad core Q6700 and Q6600 are two Core 2 cores on one chip.

The 45nm is going to be the same way. If its a dual core, its going to be "native" and if its quad its going to be 2 cores on one chip.

It does not make a damn difference if its native or not. If the performance is there then who gives a damn. It just AMD started claiming, "Well are quad cores share the same cache and are "native" and Intel's quads are not." Then every one hails AMD for there "native" design and bashes Intel for there non "native" design (not a bash to AMD as im looking foward to there new gen as its coming out in the time im building a new computer).

Ok im done ranting.

Good post,all that matters to me is performance in day to day operations.I could care less if its a 'native' design or not... native smchative,who cares !?

 

[yaric]

I think there are probably advantages either way you do it. If you spend all your time and money on making a quad core processor on one chip you might come out a little bit ahead, but that's all you have is a quad core chip. You can't break it down into a dual core or anything. By having single or dual cores you can have more versitle combinations which is probably what intel wants. I've read the thing about them wanting 32 microcores slapped into one package. Sounds like the same deal as their quad core now, and i'm sure it's pretty mega, and probably pretty cheap to put 32 small ones together than build one "native" chip with 32 cores all designed into it.

Until someone can show me that a "native" design is far superior to non "native" then i also don't give a crap...

 

[Donnie27]

OMG this native stuff is B/S.

The dual core Core 2's are "native." They share the same cache. The quad core Q6700 and Q6600 are two Core 2 cores on one chip.

The 45nm is going to be the same way. If its a dual core, its going to be "native" and if its quad its going to be 2 cores on one chip.

It does not make a damn difference if its native or not. If the performance is there then who gives a damn. It just AMD started claiming, "Well are quad cores share the same cache and are "native" and Intel's quads are not." Then every one hails AMD for there "native" design and bashes Intel for there non "native" design (not a bash to AMD as im looking foward to there new gen as its coming out in the time im building a new computer).

Ok im done ranting.

Native is just more BS Marketing from AMD. Please note, Core 2 Duo is a Native design from the Ground up Dual Core Processor. It is more modern than any of AMD K8's=P

If K8L is faster, it will because of the Core improvements AMD made, not some schlock about how Native it LOL!

 

[Mabrito]

Native is just more BS Marketing from AMD.

QFT and that is really the whole story there. Back in the PD verses X2 days, we never even heard this "native" term since the X2's were "native" and the PD were not.

Getting back on subject, please dont let this term impact your purchase go where the performace/price range is. That is what im going to end up doing. When the new AMD's come out it be during the time im building a new computer. Ill evaluate my price range, see what my options are and then choose the best one.

 

[savantu]

Core 2 Duo is more "native" than any other CPU on the market.The level of integration ( shared l2 , direct L1-to-L1 links ) is head and shoulders above AMD's crossbar.

That said , the native thing is pure BS from you know who.

I will let someone from Intel share his thoughts on the whole debate :

Lately there has been some debate about whether the Clovertown processors are native quad-core or not – “native” being equated to four cores per die. The argument often advanced by detractors is that native core may be preferable to other approaches like Intel’s MCP approach used for Clovertown processors (MCP= multi-chip package where two dual-core dies are integrated into the same package). Typical assertions are on the lines of “with native quad-core, data transfer between the cores does not need to go via the bus”.

From my perspective as an IT practitioner, the question misses the mark completely.. Processor and platform architects make different design trade-offs to optimize a whole range of attributes such as yields, performance, bin-splits, manufacturing costs, power-consumption, time-to-market and so on and ultimately the “goodness” of those trade-offs (or lack thereof) can be seen in terms of the previously listed attributes. Consequently, I would like to submit that a much more relevant question from an IT perspective is “what is the value proposition of this new quad-core processor technology relative to what is already available on the market?” or more specifically, how do the new chips compare with the existing ones from the following standpoints:

absolute performance

performance per dollar

performance per watt at various loading levels

performance per money spent on software licenses

timely availability in a server platform of your choice

….

I would argue that the criteria listed above are far more relevant than questions about isolated design decisions. Based on the “value-oriented” criteria listed above, I can confidently state that - for the vast majority of workloads (there will doubtless be exceptions) - the new Clovertown processor based servers set a whole new benchmark in terms of performance per $ and performance per watt (often 40-60% better than dual-core servers). Further, these quad-core servers constitute a veritable bonanza where software is licensed on a per-socket basis.

In closing, I would like to reiterate my invitation – take one of these out for a test drive and let us know what you think!

Sudip Chahal is a Compute and Storage architect in Intel IT.

http://blogs.intel.com/it/2006/12/quadcore_part_ii_native_or_mcp.html

 

[Scali2]

AMD's whole 'native' thing just means that they're 6 months late to the table... 6 months of no answer to Intel's quadcore at all.
Amazing that they can actually spin it so people think this is a good thing. Especially since their 'native' design isn't even guaranteed to be faster than the non-native Intels (as I said before, I don't think the shared L3-cache is all that hot, a native chip has a lot more potential).

 

[Scali2]

QFT and that is really the whole story there. Back in the PD verses X2 days, we never even heard this "native" term since the X2's were "native" and the PD were not.

The first Pentium D's (8xx series) were actually 'native' in the sense that both cores were on the same die.
Later they started the MCP concept with the 9xx series.
But go check benchmarks...You'll see little or no difference between the 8xx and 9xx series, so the MCP doesn't affect performance at all in this case.
In fact, if we disregard the fact that Pentiums have a lower performance level than Athlon64s, and look solely at the relative scaling factors in multitasking or multithreaded software, then we see that relatively speaking, the Pentium D is actually very competitive with the Athlon64 X2. It doesn't really scale worse... in fact, in some cases it may even scale slightly better.

 

[§kynet]

AMD's whole 'native' thing just means that they're 6 months late to the table... 6 months of no answer to Intel's quadcore at all.

Totally wrong. Barcelona is not late, and its intro date has nothing to do with it being a native quad core design. Period. It was always intended and designed to be native quad core from the very beginning.

The fact that it is a native quad core with IMC and HT will allow it to scale and offer virtualization that Intel cannot match. It remains to be seen if the architecture itself has what it takes of course.
Some of you Intel fanb0ys have to be the most ignorant, uninformed group anywhere. Flame away.

 

[Scali2]

Totally wrong. Barcelona is not late, and its intro date has nothing to do with it being a native quad core design. Period. It was always intended and designed to be native quad core from the very beginning.

You're missing my point.
Intel already has quadcores on the market... Even if AMD's native processor would be better, it's pretty useless because it's not out there to compete. It will be introduced at least 6 months after Intels quadcores hit the market. In the meantime Intels quadcores are completely dominating the market, because AMD's dualcores are no match for them... heck, even the 4x4 with two dualcores can't match them.
So my point is... if AMD would glue two chips together (theoretically speaking, I know it's not technically possible at this point), they'd at least have quadcores available right now.

 

[§kynet]

You're missing my point.

No, I'm not.

It will be introduced at least 6 months after Intels quadcores hit the market

This is the reality of generational products. It is not realistic to expect each company to have a next gen product at the exact same time. Naturally AMD would love to have their new chip out now, but they don't.

So my point is... if AMD would glue two chips together (theoretically speaking, I know it's not technically possible at this point), they'd at least have quadcores available right now.

Which would not be able to match anything Intel has due to the older chip architecture so what would be the point? And putting resources into making a glued together design would take resources away from Barcelona and would probably cause a delay.

Barcelona is NOT DELAYED, I have no idea where that idea comes from. If it does not hit this summer etc. and is intro'd several months later, then yes call it delayed. But as of now, the product is not delayed.

 

[Scali2]

This is the reality of generational products. It is not realistic to expect each company to have a next gen product at the exact same time. Naturally AMD would love to have their new chip out now, but they don't.

Yes, so Intel reigns supreme for half a year... not bad for a bit of copy-paste work.

Which would not be able to match anything Intel has due to the older chip architecture so what would be the point? And putting resources into making a glued together design would take resources away from Barcelona and would probably cause a delay.

AMD's dualcores don't match Intel's dualcores either... But at least it would be a bit closer than now. 4x4 is just a joke... a single-socket quadcore solution for 939 or AM2 boards would make it more affordable and more available. They might be able to have some marketshare, even though they aren't the fastest.
But currently AMD has to watch while Intel corners the entire high-end market with its fast dualcores and quadcores.

Barcelona is NOT DELAYED, I have no idea where that idea comes from. If it does not hit this summer etc. and is intro'd several months later, then yes call it delayed. But as of now, the product is not delayed.

It's not delayed, nobody said it was delayed. You might want to read more carefully.
I said AMD is 6 months late to the table... which it is, since Barcelona will be introduced 6 months later (assuming no delay).

 

[§kynet]

...But at least it would be a bit closer than now. 4x4 is just a joke... a single-socket quadcore solution for 939 or AM2 boards would make it more affordable and more available. They might be able to have some marketshare, even though they aren't the fastest..

The thing is, I don't think AMD has the resources to be screwing around with a side project to glue 2 Athlon X2's together. And if they did, it would have to be on 65nm due to power constraints, they would have to validate it on current platforms, work with mobo makers to release a compatible bios etc. This is not the design arc AMD is taking with quad core. Intel on the other hand certainly took the easy way out and just slaps 2 dies onto a wafer and calls it a day. And it works pretty well, but hardly ideal.

BTW, 4x4 is a great concept and a sound design. It was stillborn due to power problems. But the concept is good. Take the same platform, use a chipset that doesn't suck back the power and populate it with 2 Barcelona derivatives and you get an 8 core platform which should be a performance monster.

 

[Michael Daly]

I "Quad-core will again be achieved from putting two dual core Penryn cores on one package. Continuing with their somewhat criticized strategy of simply packaging multiple chips together for their Duo and Quad product lines,

The first part refers to Penryn - that's a different story than what's out now. Current C2D are two processors on a single die. Current C2Q are two C2D dies in a single package. The next C2Q iteration will be 4 processors on a single die.

Penryn is going to have to walk the same path - the first quad Penryns will be two dies in a package. Different technology means a new learning/manufacturing curve for Intel. Hence, the initial Penryns will be two die versions with single die versions later on. Penryn isn't here now, so that quote is about future tech.

The second part is BS. The current Duos are single die.

BTW - the significant advantage of one die vs two die quads is that a dual die version forces the two dies to talk to each other via the FSB (like having two C2D on a two LGA775 motherboard). If they are on a single die, they share the L2 cache and talk to each other directly, bypassing the FSB and its (potentially) slower speeds.

However, as others have pointed out, results are more important than theory and the overall design of the CPU + chipset is better for real world applications on real computers. For example, AMD states that their on-chip memory controller provides greater memory bandwidth than Intel's memory controller on the northbridge. In real world tests, the C2D is faster and that's because Intel gets better performance out of its cache, negating the importance of the memory controller location. YMMV

 

[Scali2]

The thing is, I don't think AMD has the resources to be screwing around with a side project to glue 2 Athlon X2's together. And if they did, it would have to be on 65nm due to power constraints, they would have to validate it on current platforms, work with mobo makers to release a compatible bios etc. This is not the design arc AMD is taking with quad core. Intel on the other hand certainly took the easy way out and just slaps 2 dies onto a wafer and calls it a day. And it works pretty well, but hardly ideal.

Intel can do this, because they thought ahead when designing their cores, so they can easily put multiple cores on one socket this way. Something AMD apparently overlooked.
But Intel is not calling it a day, they're still working on a single-die quadcore (and by the looks of it, it won't arrive much later than AMD's quadcore)... and with 45 nm, they will probably be able to put two of those on a single socket aswell, so the advantage remains.
It's not a side-project, it's a brilliant design strategy. They're always one step ahead of the competitor.
There's also no need for extra validation or BIOS, because the validation process is no different than when using single-die processors... they are the same dies after all.
And the BIOS will be the same as for a single-die quadcore, since as far as the motherboard is concerned, there is no difference, it's all the same socket.

Let's face it, AMD was outsmarted this time.

 

[Scali2]

BTW - the significant advantage of one die vs two die quads is that a dual die version forces the two dies to talk to each other via the FSB (like having two C2D on a two LGA775 motherboard). If they are on a single die, they share the L2 cache and talk to each other directly, bypassing the FSB and its (potentially) slower speeds.

Not necessarily.
Look at AMD's design: they have a separate HT-link for inter-CPU communication. It's perfectly possible to add an extra link to each die, so that they have a high-speed communication line besides the FSB.
In fact, it's even possible to have a single shared cache die, and have separate computing dies, and connect them all via high-speed buses. For L2 or L3 this is probably fast enough (sorta like the off-die caches back in the PII-days).

It's just that currently Intel hasn't designed its dies to be used this way yet... but there are ways to make MCP designs more efficient.

And as we see from AMD's Athlon X2 and Intels 8xx series... having everything on a single die is no guarantee that the communication is actually more efficient.

 

[§kynet]

Not necessarily.
Look at AMD's design: they have a separate HT-link for inter-CPU communication.

Maybe I'm not understanding what you're saying, but AMD's dual core chips communicate through the SRQ and crossbar, HT has nothing to do with inter core communication.

 

[Scali2]

Maybe I'm not understanding what you're saying, but AMD's dual core chips communicate through the SRQ and crossbar, HT has nothing to do with inter core communication.

Actually, I think it does, but that's for this thread: http://www.hardforum.com/showthread.php?t=1149750

What I mean is that the HT-bus is used to communicate between two physical CPUs in separate sockets... You can use a similar bus for communicating between dies in a single package. Intel could add a second bus, and use one bus to communicate between chipset and package, and the other bus to link the dies directly.

 

[§kynet]

What I mean is that the HT-bus is used to communicate between two physical CPUs in separate sockets...

ah okay. Actually I did read on another forum a few months back that AMD could actually use HT to make a glued together quad core. It is technically possible. Either way it's not going happen. Considering the performance advantage Core2 has over the X2, Intel was easily able to do a glue job. It remains to be seen if this will hurt them when Barcelona hits. I suspect that on the desktop it has minimal effect, but for the server space AMD is going to further distance themselves the higher the processor count goes. Remember, the Athlon is really an Opteron aka a server chip by design.

 

[Scali2]

ah okay. Actually I did read on another forum a few months back that AMD could actually use HT to make a glued together quad core. It is technically possible.

Not really... That is... they have the problem of each die having its own memory controller. Because they have to work on the same socket, they can only connect one controller to the outside world.
The memory controller would have to be disabled on one... Which is a bad idea... Because they will be wasting some die-space... costs more money, makes it harder to fit two dies in a single package etc...
So they'd want to redesign the dies first (which they probably have to do anyway if they want to be able to connect the HT-bus internally... and there still needs to be a HT-bus to the chipset and other sockets).

Either way it's not going happen. Considering the performance advantage Core2 has over the X2, Intel was easily able to do a glue job. It remains to be seen if this will hurt them when Barcelona hits. I suspect that on the desktop it has minimal effect, but for the server space AMD is going to further distance themselves the higher the processor count goes. Remember, the Athlon is really an Opteron aka a server chip by design.

Well, the results I've seen of the 4-CPU Xeon MP quadcore system (16 cores in total) makes it look like Core2 can go a long way with just more CPUs/dies stuck together.
I think it matters a lot less than AMD wants us to believe.
I'd say that it *could* matter more, but AMD is not good enough to design a CPU that way. They're under too much pressure, financially, economically... they *have* to put out a CPU soon.
So just like with the single-die Athlon X2, they will again not nearly reach the full potential of a native multicore processor.
Intel came a lot closer with its C2D because it had the budget and took the time.

 

[Donnie27]

Maybe I'm not understanding what you're saying, but AMD's dual core chips communicate through the SRQ and crossbar, HT has nothing to do with inter core communication.

Some friends and I talked about and concluded that that is a bad diagram. It should be;

Core0|.. Core1
L1 |.. L1
L2 |.. L2
SRI
Crossbar
IMC Link OR HT Link

For a Core0 to communicate with Core1 it has to go to SRI. On C2D Core 0 talks to Core 1. Memory access is slower but much Smarter, sure going to Main System Memory is slower. But instead of brute force, Intel went with Smart Memory so an Integrated Memory controller would have been wasted for the Desktop. Sure it would help with Multi-Socket systems. Being able to dynamically share cache so that one of the Cores can use all 4MB is cool but IMHO, smart cache and smart memory access is the REAL difference maker here. All anyone has to do is look at 6300 and 6400 C2D for proof?

Netburst Dual Cores didn't suck or didn't perform as well because their Cores weren't as good. Not to mention they had to go to the North Bridge for something as simple as Arbitration (SRQ/SRI to AMDers). Conroe has it built into the Core. If K8L were 4 K6-2 or TBird Cores with 100% of the rest of the Chip being new K8L, it would suck and get killed. K8L will be better because its CORE IMPROVEMENTS will help it, not how native it is or not. If AMD had K8L RIGHT NOW and it only consisted of 4 K8 Brisbanes Natively done as they say, it would have its ass handed to it.

 

[Michael Daly]

You can use a similar bus for communicating between dies in a single package. Intel could add a second bus, and use one bus to communicate between chipset and package, and the other bus to link the dies directly.

You're right and when I said the advantage was... I should have specified that it was an advantage for the way Intel chose to implement the interim quad vs single chip quad. When I heard that Intel was going to put two C2Ds in a single package, I assumed that they would make a fast communication bus between the dies inside the package and that was what the delays were about. I was surprised that they simply used the FSB for die-to-die comms.

 

[Bao01]

I know I've said this sometime ago when Henri Richards was still touting K8L as "evolutionary" against Core 2's "revolutionary". K8 was not designed to be multi-core. It's a server chip, and it's greatest strength is still in Hypertransport and the IMC, IOW multi-socket bandwidth.

HT and IMC combined with s940 were made for multi-sockets. s754 was a crippled version and s939 and am2 are both variants albeit, also crippled, for single sockets. This approach makes it impractical to implement multicore without a redesign.

There are a few problems with integrating two dies onto a single package.

1) There isn't enough pins to address twice the memory controllers.

2) The chipsets in all sockets can't arbitrate more memory controllers than what they were designed for.

3) Because of 1) and 2) only one memory controller per socket is allowed and that in turn necessitates the SRI/Crossbar switch. This would have been a manufacturing nightmare. A tiny SRI/Crossbar switch along with two dies must be stamped onto a pcb with precision. In addition 1 IMC is wasted. Performance along with multi-core scaling would also worsen because the separate SRI/Crossbar switch no longer is guaranteed to operate at full speed with the two cores, adding latency which is k8's bane.


But then, they could do 1) and 2) by redesigning all their chipsets and coming out with newer sockets without any guarantee of time to market, not to mention reaping the ire of partners and clients who have to start fresh again. Not a good choice. Opteron was a stable-image icon. A64 promised upgradeability. Lose these and lots of things would have gone down the drain(we're talking 2+ years ago, of course).



So yes, they did have to redesign the dies with X2. Just as they must with quad-cores. That's the key part of the "evolution". The whole "native" thing is marketing hype to cover up the fact that they really can't do it any other way.

By the looks of it, AMD is making K8L out to be the second coming. Jesus must have a hand in this. I guess you can call it "intelligent design". No wait. There's that word "evolution" again. Dang it! Blame it on Henri Richards.

Now, I'm not saying AMD is lying because their claims are indeterminate and subject to their own valuations. Besides, a lie is an intentionally misleading statement and calling it that requires one to know the other's purpose. Still, these businesses have purposes rooted in the interests of selling. Right now, AMD is not selling too well to Wall Street or Joe Blow, except at self-flagellating prices. Don't expect K8L to beat 65nm Core 2 in IPC, forget Penryn et al.(see A32 to A64, still the biggest architectural change since)


In contrast, Intel's FSB and chipsets don't have a problem handling two separate cores, at least that was the case with all recent chipsets except for i915 and i925. The Blackford chipset can actually handle 4 separate cores.

C2D was clearly designed to scale to C2Q. The shared cache makes this possible for the chipset two sync just 2 caches as it was designed for. Perhaps this is why the name Core is apt because the dual-core Core is really the core design.

The packaging also makes it possible. Sufficient pins(lands, actually) to slap two dies down and be done with it. There is absolutely no need or benefit for Intel to go to a single-die Core 2. If they do, it's because their yields are so incredibly high and they have so much excess capacity, along with capital to waste, that they can do it just to spite themselves. Not likely to happen. Maybe with Nehalem, but with Core 2, it's not necessary.

 

[§kynet]

[snip]

Most of that is the biggest bag of bullshit I've read in a long, long time. Opteron was designed from the beginning to be dual core for starters, the rest well...

 

[Scali2]

Most of that is the biggest bag of bullshit I've read in a long, long time. Opteron was designed from the beginning to be dual core for starters, the rest well...

Was it, though?
Opteron is just a variation of K8, and K8 is basically not much more than a K7 with 64-bit extensions and an integrated memory controller. So the core architecture is not fundamentally different. The K7 was obviously not designed for dualcore... and the first K8s weren't dualcore either.
Since Opteron is just an evolution of K7/K8, I don't see how it can be called 'designed to be dualcore'.
Just forget about the 'Opteron' name, it doesn't mean anything... it's just another name for the same technology.

 

[Michael Daly]

The next C2Q iteration will be 4 processors on a single die.

Penryn is going to have to walk the same path - the first quad Penryns will be two dies in a package.

I have to correct myself here. I just read an article on the web that says that Intel will not integrate a 4 processor die until Penryn and will not have a C2Q single die before then. I guess I misunderstood an earlier article I read.

 

[Donnie27]

I have to correct myself here. I just read an article on the web that says that Intel will not integrate a 4 processor die until Penryn and will not have a C2Q single die before then. I guess I misunderstood an earlier article I read.

As one guy put it best, it doesn't matter if the processors powered by Ants, all that matters is the performance to price ratio and how overclockable it is. It wouldn't matter if the processor was 4 dies on one package, if it kicked the competition's booty, then who cares?

 

[JackPack]

I have to correct myself here. I just read an article on the web that says that Intel will not integrate a 4 processor die until Penryn and will not have a C2Q single die before then. I guess I misunderstood an earlier article I read.

It's been known for a while that Nehalem will be the first monolithic quad-core product. 45nm is the "tick" of Intel's cadence model, which means the focus is on silicon process. Bloomsfield/Yorktown involves two Penryn cores packaged together.

 

[savantu]

It's been known for a while that Nehalem will be the first monolithic quad-core product. 45nm is the "tick" of Intel's cadence model, which means the focus is on silicon process. Bloomsfield/Yorktown involves two Penryn cores packaged together.

Bloomfield is Nehalem based.

 

[JackPack]

In that case, any idea what the name of the successor to Kentsfield is?

 

[Donnie27]

This is what I meant earlier LOL! You have what is really TWO WHOLE processors connected by a SRI that similar to Intel Arbitration Logic that connects TWO whole processors. What in the hell is native about that?

C2D is completely joined though. So Native to AMD is 4 whole processor connected to a Direct Connection contraption (SRI) with an added L3 Buffer. Since it's spun on the same die, it's Native? WOW! That's 4 Exec Cores, 4 L1's, 4 L2's, two memory controllers (DDR2 and DDR3, a Controller, a L3 and this Frankenprocessor is Native? I hope it kicks ass but surely someone at AMD making a lot of money can spin something out of PR than HR?

Come on AMD, treat the rest of the market like Ding Bats if you like. But for this market, treat your users like they are smart as you say they are. Talk more about the Improved ALU's, FPU, Bit and Bandwidth, smaller Gates, smarter whatever-the-hell you did to improve the processor?