BillParrish
Supreme [H]ardness
- Joined
- Aug 25, 2006
- Messages
- 7,519
For those of us that can read.
http://www.intel.com/products/chipsets/X38/index.htm
Some clues as to what the issue that delayed release:
Problem:
That first one is probally not a big deal as we will be putting 16x video cards in 99% of the time. The second one probally resulted in several large piles of worthless PCBs, ouch.
http://www.intel.com/products/chipsets/X38/index.htm
Some clues as to what the issue that delayed release:
1. PCIe 1.1 cards in PCIe slots off the MCH lead to boot failures.
Problem:
The Intel® X38 Express Chipset sets the TS1 Ordered Set - Symbol 4 Bit[6] to 1b when
a PCIe 1.1 card is plugged in. This is a reserved bit which is used in PCIe 2.0 to
a PCIe 1.1 card is plugged in. This is a reserved bit which is used in PCIe 2.0 to
broadcast support for selectable de-emphasis. PCIe 1.1 Specification states that Bit[6]
should be set to 0b. With some 2.5 GT/s PCIe 1.1 I/O cards of widths x8/x4/x1, system
restarts and hangs were exhibited during PCIe link initialization when populated in MCH
slots.
Implication:
should be set to 0b. With some 2.5 GT/s PCIe 1.1 I/O cards of widths x8/x4/x1, system
restarts and hangs were exhibited during PCIe link initialization when populated in MCH
slots.
Implication:
System unable to train some 2.5 GT/s PCIe 1.1 cards that don't comply with the PCIe
1.1 Specification. Failures have occurred across multiple vendors and different types of
1.1 Specification. Failures have occurred across multiple vendors and different types of
PCIe 1.1 cards.
Workaround:
Workaround:
Contact your Intel field representative for the latest BIOS information. Modification to
the Link Stability/Recovery Algorithm will fix this issue when using non-compliant cards
the Link Stability/Recovery Algorithm will fix this issue when using non-compliant cards
but customers should continue working with their card vendors for PCIe 1.1 Spec
compliancy.
Status:
compliancy.
Status:
No Fix. For affected steppings, see the Summary Table of Changes.
2. Intermittent IERR# hangs during cold boot does not detect PCIe
cards.
Problem:
Problem:
During cold boots, the MCH may hang during power-on and assert IERR or may not
detect PCIe cards off the primary port or secondary port. The 1.8V on-die voltage
detect PCIe cards off the primary port or secondary port. The 1.8V on-die voltage
regulator which powers the PCIe & DMI PLL may not be stable when powering on,
causing above issues.
Implication:
causing above issues.
Implication:
PLL not operating correctly could result in not detecting PCIe cards or DMI may not
operate correctly, resulting in system hang and IERR# assertion.
operate correctly, resulting in system hang and IERR# assertion.
Workaround:
Motherboard designers are required to implement board changes:
• Require 1.25V through LC filter on MCH VCCAPLL_EXT (Ball A20) & VCCAPLL_EXT2
• Require 1.25V through LC filter on MCH VCCAPLL_EXT (Ball A20) & VCCAPLL_EXT2
(Ball AR10).
• Require 1.25V on MCH VCC_EXP_PLL (Ball AB13).
• BIOS must disable 1.8V on-die VR. Contact your Intel field representative for the
latest BIOS information.
Status:
• Require 1.25V on MCH VCC_EXP_PLL (Ball AB13).
• BIOS must disable 1.8V on-die VR. Contact your Intel field representative for the
latest BIOS information.
Status:
No Fix. For affected steppings, see the Summary Table of Changes.
That first one is probally not a big deal as we will be putting 16x video cards in 99% of the time. The second one probally resulted in several large piles of worthless PCBs, ouch.