Intel resurrects the Pentium MMX for Larrabee?!

The cores on Larabee will probably be based on a simplified Banias (Pentium M) derivative, not something ancient like a Pentium MMX. :p

I makes no sense for Intel to go further back than the P6. The P5 (Pentium MMX) wasn't speed scalable and lacks the performance per clock that Larabee targets.
 
They can't be Banias cores. Intel has clearly stated that Larrabee cores are in-order cores. As the article says, the most recent in-order Intel core is the Pentium MMX.
 
caboosemoose said:
They can't be Banias cores. Intel has clearly stated that Larrabee cores are in-order cores. As the article says, the most recent in-order Intel core is the Pentium MMX.
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That's why I said simplified, not unmodified. :p

Intel is clearly capable of that task. I mentioned 2 major problems with trying to use P5 cores in Larabee above.
 
Well, either way you're tlaking major mods.

What would make more sense - gutting the Pentium M and turning it into an in-order core, or tweaking the Pentium MMX so that it clocks higher and bolting on some FP units etc?

Obviously the language I have used is a little tendentious, but the point holds - I hardly think turning Pentium M into an in-order chip obviously makes more sense than revamping the MMX core for clocks and IPC.

Discuss!
 
Each of these cores will have its own split L1 cache (instruction/data), and will support up to four simultaneous threads of execution. The cores will implement a subset of the x86 ISA that includes some GPU-specific extensions. The cores will also have a super-wide 512-bit vector FPU that's capable of processing sixteen-element floating-point vectors (single precision), along with support for control flow instructions (loops and branches) and some scalar computations.

All of the cores will also share a large pool of L2 cache. Like the number of cores, the size of this shared pool of L2 will depend on the particular product. The L2 cache will be used by the cores for communication, and there will be some kind of partitioning mechanism that will probably let a core lock a portion of the L2 that it can use for streaming data. (This would prevent a core from dirtying the L2 by moving data through the L2 rapidly.
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ARS Technica Larrabee write up and Part II, Larrabee as a GPU.
That would seem to bear little resemblance to Pentium MMX.
You're not simply going to bolt on an updated FPU and get a Larrabee core. Intel may pull some lessons from Pentium MMX and XScale and other low instruction latency, high throughput designs, but I can't imagine Larrabee will look anything like a Pentium MMX when all is out in the open.
 
Yeah, fair point - although that info from Ars doesn't sound much like a Pentium M either. I guess whatever the core is it will be fairly distant from any existing or previous core. The origins might be somewhat academic in the end.
 
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