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First lets look at the sockets intel has for nehalem's generation?
LGA1156 = 16 PCI-E, DMI, 2xDDR3
LGA1366 = 2xQPI, 3xDDR3
LGA1567 = 4QPI, 4xDDR3 (FB DIMMS)
And the chipset setups
X58 (via QPI) = Northbridge = Bridge from QPI --> PCI-E / DMI
ICH10 (via DMI) = Southbridge = extra PCI-E, SATA, USB, etc.
Now, how much do we know about sockets post lynnfield/clarkdale's generation?
The primary reason that LGA1156 exists is to bridge the gap between the current ICH10 southbridge (via DMI, aka a couple PCI-E lanes) and the onboard northbridge connections of lynnfield/havendale.
Are we expecting the 32nm shrink to convert the southbridge link to a QPI connection, or stick with DMI? It seems to me that if ICH11 had a QPI link as its connection (low latency and plenty of bandwidth) instead of DMI, the 32nm shrink derivs (codenames unknown) would suffice with 2 QPI links, PCI-E, and ram.
Bloomfield's successor could then do the same, bringing all the intel platforms to only 2 sockets (<=2 socket and >4 socket, aka 3 QPI links and 5 QPI links).
If the socket had space for 32 PCI-E, 5 QPI, and 4xDDR3, intel would need only 1 desktop socket. (Admittedly, thats a TON of pins)
Thoughts on this?
LGA1156 = 16 PCI-E, DMI, 2xDDR3
LGA1366 = 2xQPI, 3xDDR3
LGA1567 = 4QPI, 4xDDR3 (FB DIMMS)
And the chipset setups
X58 (via QPI) = Northbridge = Bridge from QPI --> PCI-E / DMI
ICH10 (via DMI) = Southbridge = extra PCI-E, SATA, USB, etc.
Now, how much do we know about sockets post lynnfield/clarkdale's generation?
The primary reason that LGA1156 exists is to bridge the gap between the current ICH10 southbridge (via DMI, aka a couple PCI-E lanes) and the onboard northbridge connections of lynnfield/havendale.
Are we expecting the 32nm shrink to convert the southbridge link to a QPI connection, or stick with DMI? It seems to me that if ICH11 had a QPI link as its connection (low latency and plenty of bandwidth) instead of DMI, the 32nm shrink derivs (codenames unknown) would suffice with 2 QPI links, PCI-E, and ram.
Bloomfield's successor could then do the same, bringing all the intel platforms to only 2 sockets (<=2 socket and >4 socket, aka 3 QPI links and 5 QPI links).
If the socket had space for 32 PCI-E, 5 QPI, and 4xDDR3, intel would need only 1 desktop socket. (Admittedly, thats a TON of pins)
Thoughts on this?
